1. Field of the Invention
This invention relates generally to the molding and encapsulation of semiconductor devices. More particularly, the invention pertains to a method and mold apparatus for encapsulating a multi-chip substrate array.
2. State of the Art
Integrated circuit semiconductor dice, sometimes referred to as chips, are manufactured from a semiconductor material such as silicon, germanium or gallium arsenide, and contain microscopic circuits which are formed on each chip by photolithographic techniques xe2x80x9cactive surfacexe2x80x9d of a semiconductor die is further formed with a plurality of external connections, typically referred to as bond pads, which are designed for soldering wire bonds and thus enable the semiconductor die to be electrically interconnected to an external electrical device, substrate or apparatus.
Present methods used in the fabrication of semiconductor die packages involve the process steps of die bonding, wire bonding, molding, deflashing, and singulation. In the die bonding process, semiconductor dice are bonded or soldered to a lead frame strip, printed wiring board, or other conductive substrate by various well-known techniques usually involving a conductive adhesive. During wire bonding, conductive wires usually formed of gold or aluminum are attached, one at a time, from bond pads on the active surface of a semiconductor die to corresponding electrode pads on the conductive substrate. Following die attach and wire bonding, a mold assembly for transfer molding is typically used for component encapsulation of individual semiconductor dice mounted on the conductive substrate, including encapsulation of the wire bond interconnections formed between the semiconductor dice and conductive substrate. In the deflashing process, resin bleed formed by mold compound that may have escaped from minute gaps between the mold assembly and the conductive substrate is removed from leads or bond pads on the conductive substrate. In the singulation process, an encapsulated semiconductor die mounted on a conductive substrate containing multiple semiconductor dice is typically isolated from other encapsulated semiconductor dice by cutting or segmenting the conductive substrate such that the electronic components comprising an individual semiconductor device package are separated from other individual semiconductor device packages.
It is well known in the art that a critical step in the semiconductor device fabrication process is the encapsulation of semiconductor dice and their interconnections. The encapsulation or xe2x80x9csealingxe2x80x9d of a semiconductor die and its wire bond interconnections within a xe2x80x9cpackagexe2x80x9d of plastic or other moldable material serves to protect their materials and components from physical and environmental stresses such as dust, heat, moisture, static electricity, and mechanical shocks.
In a typical encapsulation process for surface-mounted semiconductor dice, a conductive substrate strip, with mounted and wire bonded semiconductor dice placed along the length of the strip, is placed in the lower mold plate of a xe2x80x9csplit cavityxe2x80x9d mold comprising an upper and lower member. The upper and lower members of the mold are frequently referred to as xe2x80x9cplatensxe2x80x9d or xe2x80x9chalves.xe2x80x9d With the upper mold platen raised, the conductive substrate strip is positioned on the lower mold platen such that the component portions to be encapsulated are in registration with multiple mold cavities formed in the lower mold platen. The mold is closed when the upper platen is lowered onto the lower platen. When the mold is closed, a peripheral portion of the conductive substrate strip is typically compressed between the upper and lower platens to seal the mold cavities in order to prevent leakage of liquified plastic molding compound. The force required to compress the platens together is generally of the order of tons, even for molding machines having only a few mold cavities.
Depending upon the type of semiconductor die and substrate to be encapsulated, the upper platen may also contain mold cavities in registration with component portions of the conductive substrate strip to be encapsulated. In other devices, such as those having a heat sink attached to a semiconductor die, or in certain semiconductor dice having a ball grid array (BGA) or similar array on a circuit board, the molding process is conducted so that the outer surface of the heat sink or circuit board forms an exterior surface of the package which rests against a mold cavity or platen surface. With these semiconductor devices, the molding process may be conducted such that the exterior surface is free from coverage by the plastic encapsulant material.
Liquified encapsulant is fed to the cavities of the mold by xe2x80x9crunnersxe2x80x9d (i.e., channels) that extend the length of the conductive substrate strip. The runners, in turn, are fed from a xe2x80x9ctransfer potxe2x80x9d or reservoir which pressurizes, heats and holds the encapsulant molding compound until delivery. In some package applications, a single runner may be sufficient to supply encapsulant to feed more than one conductive substrate strip. For larger packages, however, the consumption of greater amounts of molding compound dictates that the larger package be supplied with its own dedicated runner. Usually, constricted channels known as xe2x80x9cgatesxe2x80x9d are located at the entrance to each mold cavity to limit the flow rate and injection velocity of liquified encapsulant into the cavity. Gates may be located in either the top half or bottom half of the mold, or both. If a gate is located in only one half of a mold with upper and lower cavities, a conductive substrate can be designed with an aperture extending through opposing surfaces of the conductive substrate so that the encapsulant has the ability to flow from one cavity side to the other.
Typically, preheated powdered or pelletized plastic, e.g., thermosetting resin, is placed in the transfer pot and compressed by a transfer cylinder, or ram. The heated, pressurized plastic becomes liquified and flows through the runners and gates where it eventually fills each mold cavity, thereby flowing over the semiconductor die, conductive substrate, and wire bonding areas to be encapsulated. The transfer pressures employed to push the liquified plastic through the runners, gates and into the mold cavities typically range from 200-1200 psi. This results in relatively high velocity flows out of the gates which diminish somewhat as the plastic moves into the cavity and assumes a plug-type flow configuration. Lower transfer pressures are undesirable because of the potential for polymerization or gelling of the plastic mold compound prior to completely filling the mold cavities. After the cavities are filled, the encapsulant is maintained at a specified pressure until cure.
The molding compound is then allowed a curing period, where it subsequently hardens to encapsulate the conductive substrate and the devices attached to it. Air is expelled from each cavity through one or more runners or vents as the plastic melt fills the mold cavities. Following hardening by partial cure of the thermoset plastic, the mold plates are separated along the parting line and the encapsulated semiconductor devices are removed and trimmed of excess plastic which has solidified in the runners and gates. Additional thermal treatment may complete the curing of the plastic package. The shape of the mold cavities and the configuration of the conductive substrate determine the final shape of the semiconductor package.
The molding process is then repeated with a new batch of mounted conductive substrate strips. The molding process described herein is known in the art to be subject to automation, as well as manual operation, at each phase of the molding process.
Exemplary patents describing various apparatus and methods for encapsulating surface-mount electronic packages are described by U.S. Pat. No. 6,036,908 to Nishida, U.S. Pat. No. 5,723,156 to Matumoto, U.S. Pat. No. 5,609,889 to Weber, U.S. Pat. No. 5,304,512 to Arai, U.S. Pat. No. 5,254,501 to Tung et al., U.S. Pat. No. 4,954,301 to Saeki et al., and U.S. Pat. No. 4,332,537 to Slepcevic.
At the high pressures used for delivery of encapsulant, mold cavities and their gates must be carefully designed to prevent the conductive wires from dislodging or moving into contact with one anotherxe2x80x94a condition known as wire sweep. Also factored into the design of the molding apparatus are provisions for flow characteristics sufficient to meet the essential requirement of a void-free encapsulation. A related concern in mold apparatus with upper and lower mold body cavities fed by a single gate is that when liquified plastic is transferred from the gate to the upper and lower cavities, the lower cavities tend to fill first, which can result in an upward buildup of pressure sufficient to temporarily deflect the carrier substrate during encapsulation. Upon removal from the mold plates, the residual forces from the deflection of the carrier substrate may cause cracking, spalling, etc., in the package. Controlling air bubbles is a further consideration: air bubbles potentially caused by multiple layers of wire bonding, air pockets adjacent to the semiconductor die, insufficient pressure packing, or the gasification of substrate materials due to the elevated temperatures of the transfer molding process and the like.
Several patents include disclosures which relate to solutions for conditions which cause a warping or deflection in a lead frame or other substrate during the filling of the mold cavities with liquified encapsulant. For example, U.S. Pat. No. 4,954,301 to Saeki et al. discloses a transfer cylinder whose downward displacement is controlled by a microcomputer in order to decrease void formation and deformation of the carrier insert. U.S. Pat. No. 5,723,156 to Matumoto discloses a gate arrangement designed to transfer encapsulant equally into the upper and lower cavities of the mold.
With regard to devices having an attached heat sink, U.S. Pat. No. 5,776,512 to Weber describes a mold which has a biased plug in a lower mold cavity that exerts pressure on a heat sink in contact with an upper mold half to prevent molding compound from covering the heat sink. Weber further utilizes an extending portion of the carrier substrate to contact the lower mold platen, thus stopping the carrier substrate from deflecting from the downward push of the biased plug.
U.S. Pat. No. 5,682,673 to Fehr discloses a mold for encapsulating integrated circuit chips mounted in conventional fashion to die attach pads of lead frames. The lower mold cavity of Fehr is provided with one or more installed support pins, soldered into holes in the mold, for furnishing support under the die attach pad during injection of molding compound into upper and lower mold cavities. The support pins are provided to counteract the forces resulting from the flow of encapsulant over the chip during the filling of the upper mold cavity, and thus prevent the die attach pad from undesirably contacting the lower mold cavity. In one embodiment, Fehr discloses a single support pin located directly under the center of the die attach pad. A second embodiment of Fehr shows several support pins positioned in a rectangular array under the die attach pad of a wide-area, thin package requiring increased support. The support pins of Fehr are disclosed to preferably have tapered ends of a generally conical shape to provide a small area for contact with the die attach pad.
In recent years, there has been an increased demand for high-density mounting of semiconductor packages which has coincided with advances in the performance and functionality of integrated circuits. These demands have led to numerous innovations in semiconductor die and carrier substrate design.
One form of interconnection recently developed to meet the needs of industry is known as xe2x80x9cboard-on-chipxe2x80x9d (BOC). In this arrangement, a semiconductor die (chip) is mounted, active side up, under a carrier substrate configured with one or more slots for accepting the conductive wires of the semiconductor die. The conductive wires of the semiconductor die extend through the slot in the carrier substrate where they are connected to wire bond pads of the carrier substrate""s surface.
In order to increase throughput in the mounting and encapsulation of board-on-chip devices, semiconductor dice can be mounted in various board-on-chip matrices or arrays, e.g., three devices across a width of a lead frame strip, printed wiring board or other conductive substrate, thus maximizing the number of packages to be formed per array strip. In these types of array arrangements, it may be considered advantageous, for reasons of simplicity in die tooling, molding, and economies of scale, to utilize a mold with a semiconductor die side cavity large enough to cover the entire semiconductor die side of the substrate array with encapsulant, rather than to use individual molded bodies for encapsulating each semiconductor die.
Since array-mounting does not easily allow encapsulant to be transferred from one cavity to another by flow around the substrate, both the upper and lower mold cavities may be fed encapsulant simultaneously. The relatively large semiconductor die side mold cavity area being unsupported to allow for the flow of encapsulant under the die, the problems previously discussed concerning temporary deflection of the carrier substrate during encapsulation become particularly acute in this type of board-on-chip substrate array. If no support is provided under this area, the residual forces in the substrate resulting from the deflection may, upon cure and removal of the encapsulated package from the mold plates, cause cracking, spalling, etc., in the package. Cracking and spalling are costly defects since the package""s protective abilities are compromised, and the package cannot be repaired or reworked even though an expensive semiconductor die may be inside.
Therefore, a need exists for an encapsulation method and apparatus that will allow high throughput production of reliable, high-quality semiconductor device packages from board-on-chip arrays or other conductive substrate array arrangements.
The present invention provides a mold and method suitable for the transfer molding encapsulation of a multi-chip substrate array, and the fabrication of an encapsulated semiconductor device package, while minimizing the attendant problems of voids, wire sweep and substrate deflection during encapsulant fill.
Split or injection molds can be used to achieve encapsulation of semiconductor device packages arranged on a carrier substrate with a plurality of integrated circuit semiconductor dice affixed thereto. The molds for such encapsulation are provided with cavities in each side of each respective mold half. Under the pressure of injection molding, the carrier substrate may deflect, causing voids, cracks, spalling, etc., in the package. Although deflection of the substrate depends on many factors, including, but not limited to, mold design, the primary deflection of the carrier substrate is towards the semiconductor die side of the mold, as hereinafter described.
The present invention provides an apparatus and method of encapsulating a multi-chip substrate array using transfer molding apparatus which prevents or minimizes substrate deflection into a mold cavity during encapsulant transfer. In one embodiment, a board-on-chip array is provided in which the carrier substrate is supported or otherwise fixtured during encapsulation. In this arrangement, a plurality of semiconductor dice is mounted, active side up in an array arrangement, under a carrier substrate surface. The carrier substrate is further configured with a plurality of wire bonding apertures for accepting the conductive wires of each semiconductor die. The conductive wires of each semiconductor die extend through the aperture in the carrier substrate where they are connected to wire bond pads on the carrier substrate surface. The wire bond pads on the carrier substrate surface may further be electrically connected to other conductors on the carrier substrate surface in the form of circuit traces, solder ball contact pads, and solder balls, etc. In a preferred embodiment, connective components of the conductors are arranged in a ball grid array of a preselected configuration around each aperture of the carrier substrate, the ball grid array allowing for electrical communication of the semiconductor die with external components. The carrier substrate may also be provided with alignment rails for automated transfer operations and easy mounting within the mold. The board-on-chip array is then placed in a mold assembly with a plurality of first mold cavities configured for encapsulating the electrical interconnections on the first side of the substrate, and a second mold cavity for encapsulating substantially the entire second side of the substrate, to include the plurality of array-mounted semiconductor dice.
In this aspect of the invention, substrate support elements, in the form of standoff pins or bosses, are provided for supporting the carrier substrate of the board-on-chip array during the encapsulation process. The standoff pins or bosses are configured to contact, or nearly contact, the die side area of the carrier substrate to prevent or minimize substrate deflection during the fill of the mold cavities with encapsulant material. Upon cure of the encapsulant, the carrier substrate is removed from the mold, and individual board-on-chip packages may be obtained upon segmenting the carrier substrate array.
Preferably, the standoff pins or bosses are used in a mold cavity to support the semiconductor die side of the carrier substrate. These support elements may be aligned, or non-aligned along lines representing one or more edge areas of individual board-on-chip packages. Individual chip packages may be obtained by sawing along imaginary lines extending through indentations found in the semiconductor die side of the encapsulated array, the indentations left by the aligned standoff pins or bosses during the process of substrate support. The standoff pins or bosses may be integral to the mold cavity, or may be removable. Integral standoff pins or bosses may be machined, cast, or otherwise fabricated into one or both sides of the mold. In one embodiment, the standoff pins or bosses may be resiliently mounted to a mold cavity surface to bias a substrate array against deflection during a molding process. The standoff pins or bosses preferably have elongated portions which extend outwardly from the mold cavity, and the elongated portions are preferably tapered in nature. As removable elements, the standoff pins or bosses may be incorporated into the encapsulant material of the package, once cured. The removable standoff pins or bosses may also be interlinked, and may be formed of the same, or a similar, material to that of the encapsulant.
The invention thus provides a mold and process which may be reliably used for mass production of encapsulated semiconductor packages, and which may be used in a manual or automated fashion. In one embodiment, the semiconductor packages formed by the methods of the present invention can be used to construct a semiconductor device assembly, such as a multi-chip module or a series of stacked BGA packages.
Other features and advantages of the present invention will become apparent to those of skill in the art through consideration of the ensuing description, the accompanying drawings, and the appended claims.